This invention relates to semiconductor memory devices, and more particularly to a non-volatile electrically erasable MOS memory of the floating gate type.
Electrically erasable floating gate memory devices are shown in U.S. Pat. No. 4,122,509 issued to L. S. Wall and U.S. Pat. No. 4,122,544 issued to D. S. McElroy, assigned to Texas Instruments, and in U.S. Pat. No. 3,984,822 issued to Simko et al. These devices allow electrical erasure by discharge of the floating gate through the oxide layer between the floating gate and the control gate, with proper voltages on the source, drain and control gate. One of the initial problems with these devices was overerasure, which caused the channel beneath the floating gate to go into the depletion mode so the memory transistor would conduct even with zero volts on the control gate. The structure of the McElroy patent sought to correct this problem by adding a series enhancement transistor. Even this device still exhibited problems in some conditions. First, erasure was a competing mechanism during programming because the high positive voltage in the control gate, about +25 v, plus the negative charge on the floating gate, result in fields very close to those of erase under 30 to 35 v bias. Although the ratio of the capacitance of the floating gate to control gate to the capacitance of the floating gate to the substrate could be adjusted, improving programming would degrade erase and vice versa. The result was that the programming level attained was limited by the erase mechanism, and the programming time was lengthened somewhat. A second problem was that for a very good erase mechanism, a read disturb condition was a possibility, i.e., there would be loss of electrons from a programmed floating gate, especially at higher operating voltages, for example +10 v. Third, programming difficulty occured when the floating gate was overerased too far. This occured for two reasons. One, the effective gate voltage over the floating gate channel was higher and if it got too high for a given drain voltage the programming dropped. Two, the effective drain to source voltage decreased because the floating gate channel conductance was higher compared to the series enhancement device; this too would decrease programming.
It is therefore the principal object of this invention to provide an improved electrically erasable floating gate MOS memory device. Another object is to provide a floating gate EAROM which avoids overerasure problems. A further object is to provide an EAROM cell with self-limiting erase and small cell size.